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| Austin Semiconductor, Inc. 256K x 36 SSRAM Flow-Through, Synchronous Burst SRAM FEATURES Organized 256K x 36 Fast Clock and OE\ access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-lead TQFP package for high density, high speed Low capacitive bus loading AS5SS256K36 & AS5SS256K36A PIN ASSIGNMENT (Top View) SSRAM 100-pin TQFP (DQ) (2-chip enable version, "A" indicator) SA SA ADV\ ADSP\ ADSC\ OE\ BWE\ GW\ CLK Vss VDD SA BWa\ BWb\ BWc\ BWd\ CE2 CE\ SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 OPTIONS Timing 8.5ns/10ns/100MHz 10ns/15ns/66MHz Packages 100-pin TQFP (2-chip enable) Pinout 2-chip Enables 3-chip Enables Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) MARKING -8.5* -10 DQ No. 1001 A (PRELIMINARY) no indicator XT* IT DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa 100-pin TQFP (DQ) (3-chip enable version, no indicator) SA SA ADV\ ADSP\ ADSC\ OE\ BWE\ GW\ CLK Vss VDD CE2\ BWa\ BWb\ BWc\ BWd\ CE2 CE\ SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SA SA SA SA SA SA SA NF NF VDD Vss DNU DNU SA0 SA1 SA SA SA SA MODE *NOTE: -8.5/XT combination not available. GENERAL DESCRIPTION The AS5SS256K36 employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. This 8Mb Synchronous Burst SRAM integrates a 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\). Note that CE2\ is not available on the A version. DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 For more products and information please visit our web site at www.austinsemiconductor.com AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SA SA SA SA SA SA SA SA NF VDD Vss DNU DNU SA0 SA1 SA SA SA SA MODE 1 Austin Semiconductor, Inc. GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable (OE\), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE\, is also asynchronous. WRITE cycles can be from one to four bytes wide as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP\) or address status controller (ADSC\) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV\). Address and write control are registered on-chip to AS5SS256K36 & AS5SS256K36A SSRAM simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa\ controls DQa's and DQPa; BWb\ controls DQb's and DQPb; BWc\ controls DQc's and DQPc; BWd\ controls DQd's and DQPd. GW\ LOW causes all bytes to be written. Parity bits are also featured on this device. This 8Mb Synchronous Burst SRAM operates from a +3.3V VDD power supply, and all inputs and outputs are TTLcompatible. The device is ideally suited for 486, Pentium(c), 680x0 and PowerPCTM systems and those systems that benefit from a wide synchronous data bus. FUNCTIONAL BLOCK DIAGRAM 18 SA0, SA1, SAs MODE ADV\ CLK ADDRESS REGISTER 18 SA0-SA1 16 18 BINARY COUNTER AND LOGIC CL Q1 SA1' Q0 ADSC\ ADSP\ BWd\ BYTE "d" WRITE REGISTER SA0' BYTE "d" WRITE DRIVER BWc\ BYTE "c" WRITE REGISTER BYTE "c" WRITE DRIVER 256K x 9 x 4 (x36) DQs BWb\ BYTE "b" WRITE REGISTER BYTE "b" WRITE DRIVER MEMORY ARRAY SENSE AMPS DQPa OUTPUT BUFFERS DQPb DQPc DQPd BWa\ BWE\ GW\ CE\ CE2 CE2\ OE\ BYTE "a" WRITE REGISTER ENABLE REGISTER BYTE "a" WRITE DRIVER INPUT REGISTERS 4 NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions and time diagrams for detailed information. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 Austin Semiconductor, Inc. PIN DESCRIPTION AS5SS256K36 & AS5SS256K36A SSRAM Pin Number SYMBOL TYPE DESCRIPTION 37 36 32-35, 44-50, SA0 Synchronous Address Inputs: These inputs are registered and must 81, 82, 99, SA1 Input meet the setup and hold times around the rising edge of CLK. Two 100 SA different pinouts are available for the TQFP packages. 92 (A version) 43 (3 CE version) Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times 93 BWa\ around the rising edge of CLK. A byte write enable is LOW for a WRITE 94 BWb\ Input cycle and HIGH for a READ cycle. Bwa\ controls DQa pins and DQPa; 95 BWc\ Bwb\ controls DQb pins and DQPb; Bwc\ controls DQc pins and DQPc; BWd\ 96 Bwd\ controls DQd pins and DQPd. Parity bits are featured on this device. Byte Write Enable: This active LOW input permits BYTE WRITE 87 BWE\ Input operations and must meet the setup and hold items around the rising edge of CLK. Global Write: This active LOW input allows a full 36-bit WRITE to occur 88 GW\ Input independent of the BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of CLK. Clock: CLK registers address, data, chip enable, byte write enables and 89 CLK Input burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the 98 CE\ Input device and conditions the internal use of ADSP\. CE\ is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the 92 CE2\ Input device and is sampled only when a new external address is loaded. (3 CE version) CE2\ is only available on the 3 CE version. 97 86 CE2 OE\ Input Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 83 ADV\ 85 ADSC\ Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait Input states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV\ must be HIGH at the rising edge of the first clock after an ADSP\ cycle is initiated. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be Input registered. A READ or WRITE is performed using the new address if CE\ is LOW. ADSC\ is also used to place the chip into power-down state when CE\ is HIGH. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 3 Austin Semiconductor, Inc. PIN DESCRIPTION (continued) Pin Number SYMBOL TYPE AS5SS256K36 & AS5SS256K36A SSRAM 84 ASDP\ 31 MODE 64 (a) 52, 53, 56-59, 62, 63 (b) 68, 69, 72-75, 78, 79 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 51 80 1 30 ZZ DESCRIPTION Synchronous Address Status Processor: This active LOW inputs interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of Input the byte write enables and ADSC\, but dependent upon CE\, CE2 and CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if CE2 is LOW or CE2\ is HIGH. MODE: This inputs selects the burst sequence. A LOW on this pin Input select "linear burst." NC or HIGH on this pin selects "interleaved burst." Do not alter input state while device is operating. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the Input memory array is retained. When ZZ is active, all other inputs are ignored. DQa DQb DQc DQd SRAM Data I/O's: Byte "a" is DQa pins; Byte "b" is DQb pins; Byte "c" is Input/ DQc pins; Byte "d" is DQd pins. Input data must meet setup and hold Output times around the rising edge of CLK. NC/DQPa NC/DQPb Parity Data I/Os: Byte "a" parity is DQPa; Byte "b" parity is DQPb; Byte NC/ I/O NC/DQPc "c" parity is DQPc; Byte "d" parity is DQPd. NC/DQPd Power Supply: See DC Electrical Characteristics and Operating Supply 15, 41, 65, 91 VDD Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and 4, 11, 20, 27, 54, VDDQ Supply Operating Conditions for range. 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 67, Vss Supply Ground: GND 71, 76, 90 Do Not Use: These signals may either be unconnected or wired to GND 38, 39 DNU --to improve package heat dissipation. No Connect: These signals are not internally connected and may be 16, 66 NC --connected to GND to improve package heat dissipation. No Function: These pins are internally connected to the die and have 42 the capacitance of an input pin. It is allowable to leave these pins NF --43 (A version) unconnected or driven by signals. On the 3 CE version, pin 42 is reserved as an address upgrade pin for the 16Mb Synchronous Burst. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 Austin Semiconductor, Inc. AS5SS256K36 & AS5SS256K36A SSRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS FUNCTION READ READ WRITE Byte "a" WRITE All Bytes WRITE All Bytes GW\ H H H H L BWE\ H L L L X BWa\ X H L L X BWb\ X H H L X BWc\ X H H L X BWd\ X H H L X AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 Austin Semiconductor, Inc. TRUTH TABLE OPERATION Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADDRESS CE\ CE2\ CE2 USED None H X X None L X L None L H X None L X L None L H X None X X X External L L H External L L H External L L H External L L H External L L H Next X X X Next X X X Next H X X Next H X X Next X X X Next H X X Current X X X Current X X X Current H X X Current H X X Current X X X Current H X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP\ ADSC\ X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H AS5SS256K36 & AS5SS256K36A ADV\ X X X X X X X X X X X L L L L L L H H H H H H WRITE\ X X X X X X X X L H H H H H H L L H H H H L L OE\ CLK X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D SSRAM NOTE: 1. X means "Don't Care." \ means active LOW. H Means logic HIGH. L means logic LOW. 2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\, BWc\, or BWd\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for all BWx\, BWE\, GW\ HIGH. 3. BWa\ enables WRITEs to DQa pins, DQPa. BWb\ enables WRITEs to DQb pins, DQPb. BWc\ enables WRITEs to DQc pins, DQPc. BWd\ enables WRITEs to DQd pins, DQPd. 4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be High-Z during power-up. 8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Storage Temperature (Plastics) ...........................-55C to +150C Storage Temperature (Ceramics) .........................-55C to +125C Short Circuit Output Current (per I/O)...............................100mA Voltage on any Pin Relative to Vss........................-0.5V to +4.6 V Max Junction Temperature**..............................................+150C VIN (DQx) .........................................................-0.5V to VDDQ +0.5V VIN (inputs) ................................................... ....-0.5V to VDD +0.5V AS5SS256K36 & AS5SS256K36A SSRAM *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ** Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity. 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (-55oC to +125oC or -40oC to +85oC; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) PARAMETER Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITION SYMBOL VIH VIL ILI ILO VOH VOL VDD VDDQ MIN 2.2 -0.3 -2 -2 2.4 --3.135 3.135 MAX VCC +0.3 0.8 2 2 -0.4 3.6 3.6 UNITS V V V V V V NOTES 1, 2 1, 2 3 1, 4 1, 4 1 1, 5 OV < VIN < Vcc Output(s) disabled, OV < VOUT < Vcc IOH = -4.0 mA IOL = 8.0 mA THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring (Junction to Top of Case, Top) thermal impedance, per EIA/JESD51. Thermal Resistance Thermal Resistance (Junction to Pins, Bottom) CONDITIONS 1-layer SYM JA JC TYP 40 UNITS NOTES o C/W 6 9 o C/W 6 JB 17 o C/W 6 NOTES: 1. All voltages referenced to Vss (GND). 2. Overshoot: VIH < +4.6V for t Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 Austin Semiconductor, Inc. AS5SS256K36 & AS5SS256K36A SSRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (-55oC to +125oC or -40oC to +85oC) $%& %&' 4 " / '0% " *) "*) "*) +,*) -,.* ! "# ! "# " " " () %) $ () %) $ " /'0% 1'0% " 56 78 ! ' " " 56 78 ! ' 1'0% 2& (& 3& (& ! "# %) $ ! "# ! "# 995 4 $' $' " %) $ : ; " /'0% " *) "*) "*) +,*) -,.* 1'0% 2& 3& " %) $ CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS o TA = 25 C; f = 1MHz; VDD = 3.3V SYM CI CO CA CCK MAX 4 5 3.5 3.5 UNITS pF pF pF pF NOTES 4 4 4 4 NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 3. A typical value is measured at 3.3V, 25oC and 15ns cycle time. 4. This parameter is sampled. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 Austin Semiconductor, Inc. AS5SS256K36 & AS5SS256K36A SSRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (-55oC to +125oC or -40oC to +85oC) DESCRIPTION CLOCK Clock cycle time Clock frequency Clock HIGH time Clock LOW time OUTPUT TIMES Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE\ to output valid OE\ to output in Low-Z OE\ to output in High-Z SETUP TIMES Address Address status (ADSC\, ADSP\) Address advance (ADV\) Byte write enables (BWa\ - BWd\, GW\, BWE\) Data-in Chip enable (CE\) HOLD TIMES Address Address status (ADSC\, ADSP\) Address advance (ADV\) Byte write enables (BWa\ - BWd\, GW\, BWE\) Data-in Chip enable (CE\) SYMBOL tKC tKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH 1.8 1.8 1.8 1.8 1.8 1.8 0.5 0.5 0.5 0.5 0.5 0.5 0 5.0 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 3.0 3.0 5.0 5.0 0 5.0 3.0 3.0 8.5 3.0 3.0 5.0 5.0 -8.5 MIN 10.0 100 4.0 4.0 10.0 MAX MIN 15.0 66 -10 MAX UNITS ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3, 4, 5, 6, 3, 4, 5, 6, 7 3, 4, 5, 6, 3, 4, 5, 6, 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 2 2 NOTES NOTE: 1. 2. 3. 4. 5. 6. 7. 8. at 9. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. Measured as HIGH above VIH and LOW below VIL. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O. This parameter is sampled. Transition is measured +500mV from steady state voltage. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough discussion on these parameters. OE\ is a "Don't Care" when a byte write enable is sampled LOW. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is defined by least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to remain enabled. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 9 Austin Semiconductor, Inc. AC TEST CONDITIONS Input Pulse Levels..................VIH = (VDD/2.2) +1.5V ..................VIL = (VDD/2.2) -1.5V Input rise and fall times..........................................1ns Input timing reference levels............................VDD/2.2 Output reference levels................................VDDQ/2.2 Output load.................................See Figures 1 and 2 AS5SS256K36 & AS5SS256K36A SSRAM OUTPUT LOADS +3.3v 317 DQ Z0=50 50 Vt = 1.5V DQ 351 5 pF Fig. 1 3.3V I/O OUTPUT LOAD EQUIVALENT Fig. 2 3.3V I/O OUTPUT LOAD EQUIVALENT NOTE: SRAM timing is dependent upon the capacitive loading on the outputs. AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 Austin Semiconductor, Inc. SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. AS5SS256K36 & AS5SS256K36A SSRAM ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE ELECTRICAL CHARACTERISTICS ! NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK t ZZ t RZZ ZZ t ZZI ISUPPLY t SB2 t RZZI ALL INPUTS* *Except ZZ AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 4321 321 4321 4321 4321 4 5431 2 9 541 3 54311765432121 18 91765432121 28 541 3 54391765432121 28 543 54311765432121 28 9 541 3 Don't Care 4321 4321 4321 4321 4321 4321 4321 4321 8763210987654321 54321 8763210987654321 54321 8763210987654321 54321 1 8763210987654321 54321 1 8763210987654321 54321 8763210987654321 54321 7654321 7654321 7654321 7654321 7654321 7654321 654321 654321 654321 654321 654321 654321 43210987654321 43210987654321 43210987654321 43210987654321 43210987654321 43210987654321 654321 1 1 6542109876543210987654321 321 1 221 2 6543109876543210987654321 310987654321098765432 1 6543109876543210987654321 1 2 221 6543109876543210987654321 121 6542109876543210987654321 121 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 8765432109876543212109876543210987654321098765432121098765432109876543210987654321 8765432109876543212109876543210987654321098765432121098765432109876543210987654321 8765432109876543212109876543210987654321098765432121098765432109876543210987654321 8765432109876543212109876543210987654321098765432121098765432109876543210987654321 8765432109876543212109876543210987654321098765432121098765432109876543210987654321 8765432109876543212109876543210987654321098765432121098765432109876543210987654321 4321 4321 4321 21 1 4320987654354321 0 1987654354321 24321 4320987654354321 0 1 21 1 4321987654354321 21 4320987654354321 0 21 4321 4321987654354321 1 24321 210987656543 21543 1 6 21098765432121 2432121 21098765432121 26543 1 6 21098765432121 21543 1 21098765432121 26543 21098765432121 26543 1 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 t 6542109876543210987654321 1 654321 3 1 2 6543109876543210987654321 1 221 6543109876543210987654321 310987654321098765432 121 2 6543109876543210987654321 121 2 6543109876543210987654321 121 1 221 6542109876543210987654321 121 098765432109876543212109876543210987654321098765432121098765432109876543210987687654321 54321 1 098765432109876543212109876543210987654321098765432121098765432109876543210987687654321 54321 098765432109876543212109876543210987654321098765432121098765432109876543210987687654321 54321 1 098765432109876543212109876543210987654321098765432121098765432109876543210987687654321 54321 1 098765432109876543212109876543210987654321098765432121098765432109876543210987687654321 54321 098765432109876543212109876543210987654321098765432121098765432109876543210987687654321 54321 876587654321 4321 21 876587654321 4321 876587654321 4321 3 876587654321 4321 321 876587654321 4321 321 876587654321 4321 76543214321 2765 1 7 76543214321 2765 1 76543214321 2765 1 76543214321 2165 1 76543214321 2165 7 76543214321 2765 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 1 54321 54321 54329876543254321 4321876543254321 9 1 1 54321876543254321 9 1 54321876543254321 9 1 54321876543254321 4321 1 54321 1 9 54329876543254321 1 4321 4321 4321 4321 4321 4321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 KH 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 4321 4321 4321 4321 4321 4321 BWE\, GW\, BWa\ - BWd\ ADDRESS CE\ (Note 2) ADSC\ ADSP\ ADV\ CLK OE\ t ADSS t CES t ADSH t t CEH KQLZ 2 11 21 21 321 321 21 321 21 21 21 21 21 21 21 21 21 4321 4321 4321 321 321 321 4321 4321 4321 4321 NOTE: AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2. 2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled tKQHZ after deselect. Q High-Z t AS A1 Austin Semiconductor, Inc. READ/WRITE TIMING PARAMETERS tKQHZ tKQLZ tKQ tKL tKF tKC tKH tOELZ tOEQ tKQX tOEHZ SYMBOL t KQ t AH t SINGLE READ OEQ t WS Q(A1) 10.0 MIN 3.0 3.0 3.0 3.0 t OEHZ 0 t ADSS t -8.5 t ADSH t KC t MAX 100 WH 5.0 5.0 5.0 8.5 KL A2 MIN 3.0 3.0 4.0 4.0 15 t OELZ 0 tAAH -10 READ TIMING3 tAAS Q(A2) MAX 10.0 5.0 5.0 5.0 66 t KQ tKQX UNITS MHz ns ns ns ns ns ns ns ns ns ns (Note 1) Q(A2+1) 12 tCEH tWH tAAH tADSH tAH tCES tWS tAAS tADSS tAS SYMBOL Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. MIN 0.5 0.5 0.5 0.5 0.5 1.8 1.8 1.8 1.8 1.8 ADV\ suspends burst. Q(A2+2) BURST READ -8.5 Don't Care MAX MIN 0.5 0.5 0.5 0.5 0.5 2.0 2.0 2.0 2.0 2.0 Q(A2+3) -10 MAX AS5SS256K36 & AS5SS256K36A UNITS ns ns ns ns ns ns ns ns ns ns Undefined Q(A2) Burst wraps around to its initial state SSRAM Q(A2+1) Deselect Cycle (note 4) Q(A2+2) tKQHZ 4321 321 4321 4321 4 54321 54321 54321 54321 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 4328765434321 211 391 1 2 21 4398765434321 221 21 4228765434321 211 1 9 21 4398765434321 21 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 21 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 21 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 21 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 109876543210987654321210987654321098765432109876543212109876543210987654321098763210987654321 54321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 1 54329 1 54321 9876543254321 1 54321876543254321 1 9 1 54321 1 54321 54329876543254321 1 9 54321 54321876543254321 54321876543254321 1 54329876543254321 1 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 1 4329 1 5 9876543254321 14321 4321876543254321 1 9 1 4321 1 4321 4329876543254321 1 9 54321 4321876543254321 4321876543254321 1 4329876543254321 1 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 876543210987654321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 54321 5 62 2 5432109876543210987654321321 432109876543210987654651321 6541 3541 241 2 5432109876543210987654651321 3241 5432109876543210987654651321 3241 2 2 5432109876543210987654651321 3241 5432109876543210987654321321 2 5432 43211 4321 5432 1 54320 432109876543210987654321210987654321098765432109876543254321 1 4321 5432 1 1 54321 432109876543210987654321210987654321098765432109876543243211 4321 54321 432109876543210987654321210987654321098765432109876543254321 1 54321 432109876543210987654321210987654321098765432109876543254321 4321 1 543219876543210987654321210987654321098765432109876543243211 432109876543210987654321210987654321098765432109876543254321 1 54321 14321 54329876543254321 4321876543254321 9 1 1 1 54321876543254321 9 54321876543254321 9 1 54321876543254321 4321 1 1 9 54329876543254321 14321 2109876543212 24 51 1 21098767654321 26321 21098767432121 21 56543 21098767432121 24543 51321 21098767654321 2 56543 21098767432121 21 76 51543 1 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 t WH 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 4321 4321 5 5 1 4321 4329876543254321 1 9 14321 4321876543254321 9 1876543254321 14321 4321876543254321 1 9 4321876543254321 9 1 4329876543254321 1 5432 43211 4321 4321 1 54329 4321987654324321 1 1 54321 4321987654324321 1 54321 4321987654324321 1 54321 4321987654324321 1 5432187654324321 4321987654324321 1 54321 54321 54321 54321 54321 54321 0987654321 0987654321 0987654321 0987654321 0987654321 0987654321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 1 54329876543254321 1 1 54321876543254321 54329 1 9 54321 1 54321876543254321 54329876543254321 1 1 9 54321876543254321 1 54321876543254321 1 9 54329876543254321 1 1 4321 5432 24321 1 4320987654354321 54311 21 24321 4321987654354321 5430 2 0 21 1 4321987654354321 54301 21 0 21 4321987654354321 54321 21 24321 4321987654354321 5432987654351 01 21 5430987654354321 21 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 1 92 2 98761 10987654321098765432154321 0987654321098765987154321 48761 3261 2 10987654321098765987154321 43261 2 10987654321098765987154321 43261 10987654321098765987154321 43261 2 10987654321098765432154321 2 876541 41 83 51 2 876543210987654321210987654321098765432109876587654321 3 1 47621321 3254 221 14 876543210987654321210987654321098765432109876587654321 3210987654321210987654321098765432109876543211 1 876543210987654321210987654321098765432109876587654321 1 4321 876543210987654321210987654321098765432109876587621321 1 321 4322 1 876543210987654321210987654321098765432109876587654321 121 43221 1 87687654321 54321 321 87687654321 54321 87687654321 54321 87687654321 54321 87687654321 54321 321 87687654321 54321 87654365 21 87 876543214321 2165 43214321 87 876543214321 2165 87 876543214321 2165 87 876521214321 2165 8765 876543214321 87 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 ADSP\ CLK t ADSS t ADSH Austin Semiconductor, Inc. t ADSS t KH t KC t KL WRITE TIMING ADSC\ extends burst. t ADSS 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 1 4321 4329 1 5 54321 9876543254321 4321876543254321 1 14321 4321876543254321 9 1 4329876543254321 987654321 4329876543254321 1 4321 4321 1 54321 1 1 54321 54329 1 4321 5432 9876543254321 54321876543254321 1 43211 1 54321876543254321 9 4321 1 1 54329876543254321 4321 987654324321 54329876543254321 1 54321 54321 1 4321 1 54321 54321 54321 54321 54321 54321 NOTE: BWE\ BWa\ - BWd\ AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 CE\ (See Note) ADDRESS ADSC\ ADV\ GW\ OE\ Q D 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the next internal burst address following A2. 2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. 3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV\ must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BEW\, BWa\ - BWd\ LOW. BURST READ t CES High-Z t CEH tAS A1 WRITE TIMING PARAMETERS tKH tKF tWS tAAS tADSS tOEHZ tKL tAS tKC SYMBOL t AH t OEHZ (Note 3) Single WRITE tDS tDH D(A1) 10.0 MIN 1.8 1.8 1.8 1.8 3.0 3.0 BYTE WRITE signals are ignored when ADSP\ is LOW. t ADSH -8.5 MAX 100 5.0 A2 MIN (Note 4) 2.0 2.0 2.0 2.0 4.0 4.0 15 (Note 5) -10 MAX D(A2) 5.0 66 t WS UNITS MHz t WH ns ns ns ns ns ns ns ns (Note 1) D(A2+1) 13 tDS tCEH tDH tWH tAAH tADSH tAH tCES SYMBOL Don't Care BURST WRITE D(A2+1) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. ADV\ suspends burst. MIN 0.5 0.5 0.5 0.5 0.5 0.5 1.8 1.8 -8.5 D(A2+2) MAX Undefined MIN 0.5 0.5 0.5 0.5 0.5 0.5 2.0 2.0 D(A2+3) -10 AS5SS256K36 & AS5SS256K36A MAX t ADSH A3 UNITS D(A3) t AAS ns ns ns ns ns ns ns ns t WS Extended BURST WRITE t AAH SSRAM D(A3+1) D(A3+2) 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 654321 1 6541098765432121098765432109876543210987654321 321 121 1 6543098765432121098765432109876543210987654321 3098765432121098765432109876543210987654321 121 6543098765432121098765432109876543210987654321 121 6543098765432121098765432109876543210987654321 121 6541098765432121098765432109876543210987654321 4321 1 4 432098765432121098765432109876543210987654321321 0 4321 0 4321 432198765432121098765432109876543210987654324321 1 4 4 432198765432121098765432109876543210987654324321 432198765432121098765432109876543210987654321321 0 4321 432198765432121098765432109876543210987654321321 0 1 432198765432121098765432109876543210987654324321 0 1 54321 4321 1 1 5432987654324321 9 187654324321 9 1 54329 54321 1 1 4321 5432987654324321 5432187654324321 1 1 5432187654324321 1 5432987654324321 1 54321 5 1 14321 54329876543254321 9 1 9 1 54329 54321876543254321 1 1 54321 54329876543254321 54321876543254321 1 1 54321876543254321 1 54329876543254321 1 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 87654321 87654321 87654321 87654321 87654321 87654321 87654321 543210987654321 543210987654321 543210987654321 543210987654321 543210987654321 543210987654321 543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321 654321 1 65410987687654321 210987654321 321 54321 65410987687654321 2321 54321 65410987687654321 2321 54321 65410987687654321 2321 54321 1 1 65410987687654321 2321 54321 1 65410987687654321 2321 54321 321 321 321 321 321 321 876543 1 87654 54321 21 8765432121098765432109876543210987687654321 32121098765432109876543210987687621321 1 321 54354 21 8765432121098765432109876543210987687654321 121 54321 8765432121098765432109876543210987687654321 1 54321 8765432121098765432109876543210987654321321 1 54321 8765432121098765432109876543210987687654321 1 876587654321 4321 321 321 876587654321 4321 876587654321 4321 876587654321 4321 876587654321 4321 876587654321 4321 8768432 5 87687654321 57654321 4321 321 321 87687654321 54321 87687654321 54321 87687654321 54321 1 87687654321 54321 321 321 321 321 321 321 87654321 87654321 87654321 87654321 87654321 87654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 tADSH 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 54321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 7654321 654321 654321 654321 654321 654321 654321 tKH 654321 654321 654321 654321 654321 654321 54321 54321 54321 54321 54321 54321 WEH\, WEL\, BWE\, GW\ ADDRESS ADSC\ ADSP\ CLK A1 tADSS t CES 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 654321 ADV\ CE\ (See Note) OE\ D High-Z t AS A2 t CEH Austin Semiconductor, Inc. t AH t KC t KL t OEHZ READ/WRITE TIMING3 A3 t t DS t WS WH D(A3) t DH A4 t KQ t OELZ (Note 1) 21 1 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 321 321 321 4321 4321 4321 Q Q(A1) Back-to-Back READs (Note 5) 4321 4321 4321 4321 54321 54321 54321 54321 NOTE: AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 1. 2. 3. 4. 5. Q(A4) refers to output from address A. Q(A4+1) refers to output from the next internal burst address following A4. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW. The data bus (Q) remains in High-A following a WRITE cycle unless an ADSP\, ADSC\ or ADV\ cycle is performed. GW\ is HIGH. Back-to-back READs may be controlled by either ADSP\ or ADSC\. WRITE TIMING PARAMETERS tKH tKF tADSS tKQ tKL tAS tOELZ tKC tOEHZ SYMBOL 10.0 MIN 1.8 1.8 3.0 3.0 0 -8.5 Q(A2) MAX 100 5.0 8.5 MIN 2.0 2.0 4.0 4.0 15 0 -10 SINGLE WRITE MAX 10.0 5.0 66 UNITS MHz ns ns ns ns ns ns ns ns 14 tCEH tDH tWH tADSH tAH tCES tDS tWS SYMBOL Don't Care Q(A4) Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. MIN 0.5 0.5 0.5 0.5 0.5 1.8 1.8 1.8 BURST READ Q(A4+1) -8.5 MAX Q(A4+2) Undefined MIN 0.5 0.5 0.5 0.5 0.5 2.0 2.0 2.0 -10 Q(A4+3) AS5SS256K36 & AS5SS256K36A MAX UNITS SSRAM ns ns ns ns ns ns ns ns Back-to-Back WRITEs D(A5) A5 D(A6) A6 Austin Semiconductor, Inc. MECHANICAL DEFINITIONS AS5SS256K36 & AS5SS256K36A SSRAM AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 15 Austin Semiconductor, Inc. AS5SS256K36 & AS5SS256K36A SSRAM ORDERING INFORMATION EXAMPLE: AS5SS256K36ADQ-8.5/IT Package Device Number Options** Speed ns Process Type AS5SS256K36 A DQ -8.5 /* AS5SS256K36 A DQ -10 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing **DEFINITION OF OPTIONS 2-Chip Enable Pinout 3-Chip Enable Pinout NOTES: 1. -8.5/XT combination not available. -40oC to +85oC1 -55oC to +125oC -55oC to +125oC A no indicator AS5SS256K36 & AS5SS256K36A Rev. 3.6 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 16 |
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